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008			210106s2021 si a o |||| 0|eng d
020			_a9789813346420
024	7		_a10.1007/978-981-33-4642-0 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _erda _dES-MaUEC
050		4	_aTK7888.4 _b2021 EB
100	1		_aTaraate, Vaibbhav _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9100582
245	1	0	_aASIC Design and Synthesis : _bRTL Design Using Verilog _cby Vaibbhav Taraate.
250			_aFirst edition 2021
264		1	_aSingapore _bSpringer International Publishing _c2021
300			_a1 recurso en línea (XXI, 330 páginas) _b311 ilustraciones, 184 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aarchivo de texto _bPDF
490	0		_aEngineering (SpringerNature-11647)
490	0		_aEngineering (R0) (SpringerNature-43712)
505	0		_aChapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520	3		_aThis book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
988			_aSpringer_Engineering_2021
650		7	_2embne _aOrdenadores _9138111
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-33-4642-0 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b03/2021 _dz _eb _zSI