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008			200610s2020 si a o |||| 0|eng d
020			_a9789811544057
024	7		_a10.1007/978-981-15-4405-7 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7885.7 _b2020 EB
100	1		_aTaraate, Vaibbhav _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9100582
245	1	0	_aSystemVerilog for Hardware Description _bRTL Design and Verification _cby Vaibbhav Taraate
250			_aFirst edition
264		1	_aSingapore _bSpringer Singapore : _bImprint: Springer _c2020
300			_a1 recurso en línea (XXI, 252 páginas) _b104 ilustraciones, 95 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aArchivo de texto _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aChapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.
520	3		_aThis book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
988			_aSpringer_Engineering_23062020
650		7	_2embne _9150789 _aLenguajes de descripción del soporte físico
650		7	_2embne _9668846 _aVERILOG (Lenguaje de descripción del soporte físico)
710	2		_aSpringerLink (Online service) _0http://id.loc.gov/authorities/names/no2005046756 _1http://viaf.org/viaf/148105729
776	0	8	_iPrinted edition: _z9789811544040
776	0	8	_iPrinted edition: _z9789811544064
776	0	8	_iPrinted edition: _z9789811544071
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-15-4405-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b06/2020 _dz _eIG _zSI