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999			_c120299 _d120299
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003			ES-MaUEC
005			20230102114034.0
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007			cr nn nnnaamaa
008			200504s2020 gw a o |||| 0|eng d
020			_a9783030442828
024	7		_a10.1007/978-3-030-44282-8 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTS171.8 _b2020 EB
100	1		_aGoli, Mehran _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/2158259333302302074 _9675064
245	1	0	_aAutomated Analysis of Virtual Prototypes at the Electronic System Level : _bDesign Understanding and Applications / _cMehran Goli, Rolf Drechsler
250			_aFirst edition
264		1	_aCham _bSpringer International Publishing : _bImprint: Springer _c2020
300			_a1 recurso en línea (XXI, 166 páginas) _b53 ilustraciones
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aArchivo de texto _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aChapter 1. Introduction -- Chapter 2. Background -- Chapter 3. Design Understanding Methodology -- Chapter 4. Application I: Verification -- Chapter 5. Application II: Security Validation -- Chapter 6. Application III: Design Space Exploration -- Chapter 7. Conclusion.
520	3		_aThis book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process. Provides an extensive introduction to the field of SystemC‐based virtual prototype (VP) analysis at the electronic system level; Describes a design understanding methodology from both debugger-based and compiler‐based perspectives; Illustrates a semi‐formal verification approach to check the validity of a given VP against its specification, user‐defined rules and protocol; Discusses a security validation approach to validate the run‐time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity); Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels.
988			_aSpringer_Engineering_23062020
650		7	_aPrototipos _2embne _9669967
650		7	_aElectrónica _2embne _9138690
700	1		_aDrechsler, Rolf _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/n98033803 _1http://viaf.org/viaf/64793347 _999112
710	2		_aSpringerLink (Online service) _0http://id.loc.gov/authorities/names/no2005046756 _1http://viaf.org/viaf/148105729
776	0	8	_iPrinted edition: _z9783030442811
776	0	8	_iPrinted edition: _z9783030442835
776	0	8	_iPrinted edition: _z9783030442842
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-44282-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b07/2020 _dz _eo _zSI