000			04182nam a2200445 i 4500
710	2		_aSpringerLink (Online service) _9106996
999			_c119325 _d119325
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003			ES-MaUEC
005			20230102113942.0
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007			cr nn nnnaamaa
008			200227s2020 gw | s |||| 0|eng d
020			_a9783030387969
024	7		_a10.1007/978-3-030-38796-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7868.D5 _b2020 EB
100	1		_aJain, Saurabh _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9672641
245	1	0	_aAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling : _bFrom the Clock Path to the Data Path _cby Saurabh Jain, Longyang Lin, Massimo Alioto.
250			_aFirst edition 2020.
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XVI, 166 páginas) _b113 ilustraciones, 106 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aArchivo de texto _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction to wide voltage scaling, applications and challenges -- Reconfigurable microarchitectures down to pipestage and memory bank level -- Automated design flows and run-time optimization for reconfigurable microarchitectures -- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories -- Reconfigurable clock networks, automated design flows, run-time optimization and case study -- Conclusion.
520	3		_aThis book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained. Provides extensive coverage of the challenges and the key technologies enabling wide power-performance range in digital sub-systems (e.g., processors, memories, accelerators); Includes in-depth description of silicon-proven methodologies to design reconfigurable data path and clock path; Describes techniques for reconfigurable microarchitectures, down to the pipestage and the clock repeater level; Uses a highly interdisciplinary approach covering the circuit, the microarchitectural and the system levels of abstraction; Presents practical design examples and the related methodologies; Offers complementary design files and scripts, useful to replicate the presented developments and develop new designs.
988			_aSpringer_Engineering_31032020
650		7	_2embne _aElectrónica digital _9141102
700	1		_aLin, Longyang _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9673503
700	1		_aAlioto, Massimo _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9673504
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783030387952
776	0	8	_iPrinted edition: _z9783030387976
776	0	8	_iPrinted edition: _z9783030387983
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-38796-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2020 _dz _ek _zSI