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710	2		_aSpringerLink (Online service) _9106996
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007			cr nn nnnaamaa
008			200320s2020 gw | s |||| 0|eng d
020			_a9783030415365
024	7		_a10.1007/978-3-030-41536-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874 _b2020 EB
100	1		_aCanelas, António Manuel Lourenço _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9673410
245	1	0	_aYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies _cby António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta
250			_aFirst edition 2020.
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XXIII, 237 páginas) _b139 ilustraciones, 97 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_aArchivo de texto _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.
520	3		_aThis book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.
988			_aSpringer_Engineering_31032020
650		7	_2embne _aCircuitos integrados _xDiseño y construcción _9179611
700	1		_aCorreia Guilherme, Jorge Manuel _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9673411
700	1		_aHorta, Nuno C. G. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _9677277
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783030415358
776	0	8	_iPrinted edition: _z9783030415372
776	0	8	_iPrinted edition: _z9783030415389
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-41536-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2020 _dz _ek _zSI