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999			_c118259 _d118259
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005			20230102113852.0
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007			cr nn nnnaamaa
008			191220s2020 gw a o |||| 0|eng d
020			_a9783030313104
024	7		_a10.1007/978-3-030-31310-4 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK5105.546 _b2020 EB
100	1		_aManna, Kanchan _9673166
245	1	0	_aDesign and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures _cby Kanchan Manna, Jimson Mathew
250			_aPrimera edición 2020
264		1	_aCham _bSpringer _c2020
300			_a1 recurso en línea (XII, 162 páginas) _b 31 ilustraciones, 8 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction to Network-on-Chip Designs and Tests -- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems -- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems -- Temperature-aware design strategy for 3D-NoC-based multicore systems -- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.
520	3		_aThis book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.
988			_aPrimersemestre_2020_Engineering
650		7	_2embne _aRedes informáticas _9141354
700	1		_aMathew, Jimson _eautor
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783030313098
776	0	8	_iPrinted edition: _z9783030313111
776	0	8	_iPrinted edition: _z9783030313128
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-31310-4 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b04/2019 _dz _eu _zSI