000			03225nam a2200445 c 4500
710	2		_aSpringerLink (Online service) _9106996
999			_c118166 _d118166
001			118166
003			ES-MaUEC
005			20230102113847.0
006			a||||fo|||| 00| 0
007			cr nn nnnaamaa
008			191122s2020 gw a o |||| 0|eng d
020			_a9783030305963
024	7		_a10.1007/978-3-030-30596-3 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7895 .E42 _b2020 EB
100	1		_aFarahmandi, Farimah _9673242
245	1	0	_aSystem-on-Chip Security : _bValidation and Verification _cby Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra
250			_aPrimera edición 2020
264		1	_aCham _bSpringer _c2020
300			_a1 recurso en línea (XIX, 289 páginas) _b 105 ilustraciones, 78 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
505	0		_aIntroduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.
520	3		_aThis book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.
988			_aPrimersemestre_2020_Engineering
650		7	_2embne _9667201 _aSistemas embebidos _xMedidas de seguridad
700	1		_aHuang, Yuanwen. _eautor
700	1		_aMishra, Prabhat. _eautor
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783030305956
776	0	8	_iPrinted edition: _z9783030305970
776	0	8	_iPrinted edition: _z9783030305987
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-30596-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b04/2020 _dz _eu _zSI