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005			20230102113846.0
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008			191211s2020 gw a o |||| 0|eng d
020			_a9783030357436
024	7		_a10.1007/978-3-030-35743-6 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874 _b2020 EB
100	1		_aRosa, João P. S. _9673240
245	1	0	_aUsing Artificial Neural Networks for Analog Integrated Circuit Design Automation _cby João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço
250			_aPrimera edición 2020
264		1	_aCham _bSpringer _c2020
300			_a1 recurso en línea (XVIII, 101 páginas)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aSpringerBriefs in Applied Sciences and Technology _x2191-530X
505	0		_aIntroduction -- Related Work -- Overview of Artificial Neural Networks (ANNs) -- On the Exploration of Promising Analog IC Designs via ANNs -- ANNs as an Alternative for Automatic Analog IC Placement -- Conclusions. .
520	3		_aThis book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices' sizes to circuits' performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices' sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit's performances as input features and devices' sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. .
988			_aPrimersemestre_2020_Engineering
650		7	_2embne _aCircuitos integrados _xDiseño y construcción _9179611
700	1		_aGuerra, Daniel J. D. _eautor
700	1		_aHorta, Nuno C. G. _eautor
700	1		_aMartins, Ricardo M. F. _eautor
700	1		_aLourenço, Nuno C. C. _eautor
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783030357429
776	0	8	_iPrinted edition: _z9783030357443
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-35743-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b04/2020 _dz _eu _zSI