000			02550nam a2200433 i 4500
710	2		_aSpringerLink (Online service) _9106996
999			_c118097 _d118097
001			118097
003			ES-MaUEC
005			20230102113843.0
006			a||||fo|||| 00| 0
007			cr nn nnnaamaa
008			200102s2020 si a o |||| 0|eng d
020			_a9789811513145
024	7		_a10.1007/978-981-15-1314-5 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
041	0		_aeng
050		4	_aTK7895.E42 _b2020 EB
100	1		_aTaraate, Vaibbhav _eautor _9100582
245	1	0	_aLogic Synthesis and SOC Prototyping : _bRTL Design using VHDL _cby Vaibbhav Taraate.
250			_aFirst edition
264		1	_aSingapore _bSpringer Singapore : _bImprint Springer _c2020
300			_a1 recurso en línea (XIX, 251 páginas)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
505	0		_aIntroduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA. .
520	3		_aThis book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
988			_aPrimersemestre_2020_Engineering
650		7	_2embne _aSistemas embebidos _9667201
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9789811513138
776	0	8	_iPrinted edition: _z9789811513152
776	0	8	_iPrinted edition: _z9789811513169
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-15-1314-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b03/2020 _dz _eb _zSI