000			04000nam a2200397 c 4500
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988			_aSpringer_Engineering_2020
999			_c114570 _d114570 _x1
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008			191009s2020 gw a o |||| 0|eng d
020			_a9783030247379
024	7		_a10.1007/978-3-030-24737-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7885.7 _b2020 EB
100	1		_aMehta, Ashok B. _eautor _998903
245	1	0	_aSystem Verilog Assertions and Functional Coverage : _bGuide to Language, Methodology and Applications _cby Ashok B. Mehta.
250			_a3rd ed. 2020.
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XXXIX, 507 páginas) _b 270 ilustraciones, 258 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options.
520	3		_aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. · Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; · Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; · Explains each concept in a step-by-step fashion and applies it to a practical real life example; · Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.
650		7	_2embne _9668846 _aVERILOG (Lenguaje de descripción del soporte físico)
776	0	8	_iPrinted edition: _z9783030247362
776	0	8	_iPrinted edition: _z9783030247386
776	0	8	_iPrinted edition: _z9783030247393
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-24737-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
998			_aSI _cm _dz _feng _ggw _h0 _b12/2019 _ek _zSI