000			02921nam a2200433 c 4500
942			_2lcc _cLE
988			_aSpringer_Engineering_2020
999			_c114556 _d114556 _x1
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003			ES-MaUEC
005			20230110040226.0
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007			cr nn nnnaamaa
008			190904s2020 gw a o |||| 0|eng d
020			_a9783030153342
024	7		_a10.1007/978-3-030-15334-2 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7868.L6 _b2020 EB
100	1		_aYasin, Muhammad _eautor _9671550
245	1	0	_aTrustworthy Hardware Design : _bCombinational Logic Locking Techniques _cby Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu.
250			_a1st ed. 2020.
264		1	_aCham _bSpringer International Publishing _c2020
300			_a1 recurso en línea (XXI, 142 páginas) _b65 ilustraciones, 58 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aAnalog Circuits and Signal Processing _x1872-082X
490	0		_aEngineering (Springer-11647)
505	0		_aThe Need for Logic Locking -- A Brief History of Logic Locking -- Pre-SAT Logic Locking -- The SAT Attack -- Post-SAT 1: Point function-based Logic Locking -- Approximate Attacks -- Structural Attacks -- Post-SAT 2: Insertion of SAT-unresolvable Structures -- Post-SAT 3: Stripped-Functionality Logic Locking.
520	3		_aWith the popularity of hardware security research, several edited monograms have been published, which aim at summarizing the research in a particular field. Typically, each book chapter is a recompilation of one or more research papers, and the focus is on summarizing the state-of-the-art research. Different from the edited monograms, the chapters in this book are not re-compilations of research papers. The book follows a pedagogical approach. Each chapter has been planned to emphasize the fundamental principles behind the logic locking algorithms and relate concepts to each other using a systematization of knowledge approach. Furthermore, the authors of this book are in a good position to be able to deliver such a book, as they contributed to this field significantly through numerous fundamental papers.
650		7	_2embne _aCircuitos lógicos _9139135
700	1		_aRajendran, Jeyavijayan (JV) _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aSinanoglu, Ozgur _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iPrinted edition: _z9783030153335
776	0	8	_iPrinted edition: _z9783030153359
776	0	8	_iPrinted edition: _z9783030153366
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-15334-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
998			_aSI _cm _dz _feng _ggw _h0 _b11/2019 _ek _zSI