000			03615nam a22004335i 4500
710	2		_aSpringerLink (Online service) _9106996
999			_c110970 _d110970
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008			190530s2019 gw a o |||| 0|eng d
020			_a9783030207212
024	7		_a10.1007/978-3-030-20721-2 _2doi
040			_bspa _dES-MaUEC _cES-MaUEC
050		4	_aTK7895.G36 _b2019 EB
100	1		_aSkliarova, Iouliia _eautor _9671164
245	1	0	_aFPGA-BASED Hardware Accelerators _cby Iouliia Skliarova, Valery Sklyarov.
264		1	_aCham _bImprint: Springer _c2019
300			_a1 recurso en línea (XVI, 245 páginas)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _asin mediación _bn
338			_2rdacarrier _avolumen _bnc
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
490	0		_aLecture Notes in Electrical Engineering _x1876-1100 _v566
505	0		_aReconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.
520	3		_aThis book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.
650		7	_2embne _aDispositivos FPGAs _9667973
650		7	_2embne _aIngeniería de sistemas _9138451
700	1		_aSklyarov, Valery. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iPrinted edition: _z9783030207205
776	0	8	_iPrinted edition: _z9783030207229
776	0	8	_iPrinted edition: _z9783030207236
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-20721-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aPrimersemestre_2019_Engineering
998			_aSI _cm _dz _feng _ggw _h0 _b10/2019 _ek _zSI