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710	2		_aSpringerLink (Online service) _9106996
999			_c110872 _d110872
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005			20230102113442.0
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020			_a9783030032388
024	7		_a10.1007/978-3-030-03238-8 _2doi
040			_bspa _dES-MaUEC _cES-MaUEC
050		4	_aTK7874.75 _b2019 EB
100	1		_aLee, Weng Fook _eautor _9671173
245	1	0	_aLearning from VLSI Design Experience _cby Weng Fook Lee.
264		1	_aCham _bImprint: Springer _c2019
300			_a1 recurso en línea (XXIX, 214 páginas) _b141 ilustraciones, 55 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aChapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. .
520	3		_aThis book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience.
650		7	_2embne _9669585 _aCircuitos integrados VLSI _xDiseño
776	0	8	_iPrinted edition: _z9783030032371
776	0	8	_iPrinted edition: _z9783030032395
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-03238-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aPrimersemestre_2019_Engineering
998			_aSI _cm _dz _feng _ggw _h0 _b10/2019 _ek _zSI