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020			_a9789811087769
024	7		_a10.1007/978-981-10-8776-9 _2doi
040			_bspa _dES-MaUEC _cES-MaUEC
050		4	_aTK7895.E42 _b2019 EB
100	1		_aTaraate, Vaibbhav _eautor _9100582
245	1	0	_aAdvanced HDL Synthesis and SOC Prototyping : _bRTL Design Using Verilog _cby Vaibbhav Taraate.
264		1	_aSingapore _bImprint: Springer _c2019
300			_a1 recurso en línea (XXI, 307 páginas) _b263 ilustraciones, 196 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520	3		_aThis book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
650		7	_2embne _aCircuitos integrados _9139614
650		7	_2embne _9668846 _aVERILOG (Lenguaje de descripción del soporte físico)
776	0	8	_iPrinted edition: _z9789811087752
776	0	8	_iPrinted edition: _z9789811087776
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-10-8776-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aPrimersemestre_2019_Engineering
998			_aSI _cm _dz _feng _ggw _h0 _b10/2019 _ek _zSI