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710	2		_aSpringerLink (Online service) _9106996
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020			_a9783319981161
024	7		_a10.1007/978-3-319-98116-1 _2doi
040			_bspa _dES-MaUEC _cES-MaUEC
050		4	_aQA76.9 .D43 _b2019 EB
245	0	0	_aPost-Silicon Validation and Debug _cedited by Prabhat Mishra, Farimah Farahmandi
264		1	_aCham _bSpringer International Publishing ; _bImprint: Springer _c2019
300			_a1 recurso en línea (XV, 394 páginas) _b189 ilustraciones, 113 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aPart 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug.
520	3		_aThis book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs.
988			_aPrimersemestre_2019_Engineering
650		7	_2embne _9670306 _aDepuración (Informática)
700	1		_aFarahmandi, Farimah. _eeditor literario
700	1		_aMishra, Prabhat. _eeditor literario
776	0	8	_iPrinted edition: _z9783030074548
776	0	8	_iPrinted edition: _z9783319981154
776	0	8	_iPrinted edition: _z9783319981178
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-98116-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_aSI _cm _dz _feng _ggw _h0 _b08/2019 _eu _zSI