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020 _a9783319955131
024 7 _a10.1007/978-3-319-95513-1
_2doi
040 _bspa
_dES-MaUEC
_cES-MaUEC
050 4 _aQA76
_b2019 EB
100 1 _aRussinoff, David M.
_eautor
245 1 0 _aFormal Verification of Floating-Point Hardware Design :
_bA Mathematical Approach
_cby David M. Russinoff.
264 1 _aCham
_bSpringer International Publishing :
_bImprint: Springer
_c2019.
300 _a1 recurso en línea (XXIV, 382 páginas)
_b 32 ilustraciones
336 _2rdacontent
_aTexto
_btxt
337 _2rdamedia
_aelectrónico
_bc
338 _2rdacarrier
_arecurso electrónico
_bcr
347 _atext file
_bPDF
490 0 _aEngineering (Springer-11647)
505 0 _a1 Basic Arithmetic Functions -- 2 Bit Vectors -- 3 Logical Operations -- 4 Floating-Point Numbers -- 5 Floating-Point Formats -- 6 Rounding -- 7 IEEE-Compliant Square Root -- 8 Addition -- 9 Multiplication -- 10 SRT Division and Square Root -- 11 FMA-Based Division -- 12 SSE Floating-Point Instructions -- 13 x87 Instructions -- 14 Arm Floating-Point Instructions -- 15 The Modeling Language -- 16 Double-Precision Multiplication -- 17 Double-Precision Addition and FMA -- 18 Multi-Precision Radix-4 SRT Division -- 19 Multi-Precision Radix-4 SRT Square Root.
520 3 _aThis is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The book consists of five parts, the first two of which present a rigorous exposition of the general theory based on the first principles of arithmetic. Part I covers bit vectors and the bit manipulation primitives, integer and fixed-point encodings, and bit-wise logical operations. Part II addresses the properties of floating-point numbers, the formats in which they are encoded as bit vectors, and the various modes of floating-point rounding. In Part III, the theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, Part IV contains high-level specifications of correctness of the basic arithmetic instructions of several major industry-standard floating-point architectures, including all details pertaining to the handling of exceptional conditions. Part V illustrates the methodology, applying the preceding theory to the comprehensive verification of a state-of-the-art commercial floating-point unit. All of these results have been formalized in the logic of the ACL2 theorem prover and mechanically checked to ensure their correctness. They are presented here, however, in simple conventional mathematical notation. The book presupposes no familiarity with ACL2, logic design, or any mathematics beyond basic high school algebra. It will be of interest to verification engineers as well as arithmetic circuit designers who appreciate the value of a rigorous approach to their art, and is suitable as a graduate text in computer arithmetic.
650 7 _aOrdenadores
_2embne
_9138111
650 7 _aDiseño de sistemas
_2embne
_9158356
776 0 8 _iPrinted edition:
_z9783030070489
776 0 8 _iPrinted edition:
_z9783319955124
776 0 8 _iPrinted edition:
_z9783319955148
856 4 0 _uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-95513-1
_zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942 _2lcc
_cLE
988 _aPrimersemestre_2019_Engineering
998 _aSI
_b08/2019
_cm
_dz
_ea
_feng
_ggw
_h0