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| 006 | a||||fo|||| 00| 0 | ||
| 007 | cr nn nnnaamaa | ||
| 710 | 2 |
_aSpringerLink (Online service) _9106996 |
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| 999 |
_c110502 _d110502 _x1 |
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| 001 | 110502 | ||
| 003 | ES-MaUEC | ||
| 005 | 20230102113424.0 | ||
| 008 | 190130s2019 gw a o |||| 0|eng d | ||
| 020 | _a9783030109585 | ||
| 024 | 7 |
_a10.1007/978-3-030-10958-5 _2doi |
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| 040 |
_bspa _dES-MaUEC _cES-MaUEC |
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| 050 | 4 |
_aTK7872 .P38 _b2019 EB |
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| 245 | 0 | 0 |
_aDigital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission _cNereo Markulic [y otros tres] |
| 264 | 1 |
_aCham _bSpringer International Publishing : _bImprint: Springer _c2019 |
|
| 300 |
_a1 recurso en línea (XXIII, 138 páginas) _b97 ilustraciones |
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| 336 |
_2rdacontent _aTexto _btxt |
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| 337 |
_2rdamedia _aelectrónico _bc |
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| 338 |
_2rdacarrier _arecurso electrónico _bcr |
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| 347 |
_atext file _bPDF |
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| 490 | 0 |
_aAnalog Circuits and Signal Processing _x1872-082X |
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| 490 | 0 | _aEngineering (Springer-11647) | |
| 505 | 0 | _aChapter 1. Introduction -- Chapter 2. A Digital-to-Time Converter based Subsampling PLL for Fractional Synthesis -- Chapter 3. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation -- Chapter 4. A Background-Calibrated Digital Subsampling Polar Transmitter -- Chapter 5. Conclusion and Future Outlook. | |
| 520 | 3 | _aThis book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today's art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards. Guides development of DTC-based Fractional-N Subsampling PLL and Subsampling Polar Transmitters, covering material from fundamental theory, over system level considerations to building block IC implementation; Describes a fully background-calibrated environment that can used in general context of fractional frequency synthesis and/or phase/frequency modulation; Presents three IC implementations, showing system level analysis, design methodology, circuit details and measurement results. | |
| 988 | _aPrimersemestre_2019_Engineering | ||
| 650 | 7 |
_2embne _aElectrónica _xAparatos e instrumentos _9138690 |
|
| 650 | 7 |
_2embne _aProcesadores digitales de señal _9162764 |
|
| 700 | 1 |
_aMarkulic, Nereo _eautor _9670194 |
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| 776 | 0 | 8 |
_iPrinted edition: _z9783030109578 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030109592 |
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-030-10958-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
| 942 |
_2lcc _cLE |
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| 998 |
_aSI _cm _dz _feng _ggw _h0 _b07/2019 _eel _zSI |
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