000			03493nam a22004455i 4500
710	2		_aSpringerLink (Online service) _9106996
999			_c110412 _d110412 _x1
001			110412
003			ES-MaUEC
005			20230102113419.0
006			a||||fo|||| 00| 0
007			cr nn nnnaamaa
008			181023s2019 gw a o |||| 0|eng d
020			_a9783319992235
024	7		_a10.1007/978-3-319-99223-5 _2doi
040			_bspa _dES-MaUEC _cES-MaUEC
050		4	_aLB1065 _b2019 EB
100	1		_aMoons, Bert _eautor _9670070
245	1	0	_aEmbedded Deep Learning : _bAlgorithms, Architectures and Circuits for Always-on Neural Network Processing _cBert Moons, Daniel Bankman, Marian Verhelst
264		1	_aCham _bSpringer International Publishing : _bImprint: Springer _c2019
300			_a1 recurso en línea (XVI, 206 páginas) _b124 ilustraciones
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aChapter 1 Embedded Deep Neural Networks -- Chapter 2 Optimized Hierarchical Cascaded Processing -- Chapter 3 Hardware-Algorithm Co-optimizations -- Chapter 4 Circuit Techniques for Approximate Computing -- Chapter 5 ENVISION: Energy-Scalable Sparse Convolutional Neural Network Processing -- Chapter 6 BINAREYE: Digital and Mixed-signal Always-on Binary Neural Network Processing -- Chapter 7 Conclusions, contributions and future work
520	3		_aThis book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy - applications, algorithms, hardware architectures, and circuits - supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization's implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts
650		7	_2embne _9147743 _aMotivación en educación
650		7	_2embne _9150143 _aEstrategias de aprendizaje
650		7	_2embne _aEducación _xProceso de datos
700	1		_aBankman, Daniel. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aVerhelst, Marian. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iPrinted edition: _z9783030075774
776	0	8	_iPrinted edition: _z9783319992228
776	0	8	_iPrinted edition: _z9783319992242
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-99223-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
988			_aPrimersemestre_2019_Engineering
998			_aSI _cm _dz _feng _ggw _h0 _b07/2019 _eel _zSI