000			03030nam a22003495i 4500
001			104064
003			DE-He213
005			20230102113158.0
007			cr nn 008mamaa
008			140821s2015 gw | s |||| 0|eng d
020			_a9783319076119
024	7		_a10.1007/978-3-319-07611-9 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC
050		4	_aTK7888.4 2015 EB
100	1		_aSalah, Khaled _eautor _9669766
245	1	0	_aArbitrary Modeling of TSVs for 3D Integrated Circuits _cby Khaled Salah, Yehea Ismail, Alaa El-Rouby.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (IX, 179 páginas 159 ilustraciones, 99 ilustraciones a color.)
490	0		_aAnalog Circuits and Signal Processing _x1872-082X
505	0		_aIntroduction: Work around Moore's Law -- 3D/TSV Enabling Technologies -- TSV Modeling and Analysis -- TSV Verification -- TSV Macro-Modeling Framework -- TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications and TSV-Based Bandpass Filter -- Imperfection in TSV Modeling -- New Trends in TSV -- TSV Fabrication -- Conclusions.
520	3		_aThis book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance, and nearby contact effects.  Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis, and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor,  and inductive-based communication system, and bandpass filtering. ·Introduces a robust model that captures accurately all the loss modes of a TSV,  coupling parasitics between TSVs and the TSV nonlinear capacitance and resistance of the depletion region; ·Enables readers to use a model which is technology dependent and can be used for any TSV configuration; ·Reveals a novel on-chip wireless communication technique, based on TSV spiral inductors; ·Equips readers for fast parasitic extraction of TSVs for 3D IC design.
650		7	_aCircuitos integrados _xDiseño y construcción _2embne _9179611
700	1		_aIsmail, Yehea _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/52914444/
700	1		_aEl-Rouby, Alaa _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iEdición impresa: _z9783319076102
776	0	8	_iEdición impresa: _z9783319076126
776	0	8	_iEdición impresa: _z9783319374970
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-07611-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
490	0		_aEngineering (Springer-11647)
988			_aEBSPRINGER_2018
998			_b06/2019 _dz _ek _feng _ggw _h0
999			_c104064 _d104064 _x1