000			03243nam a22003255i 4500
001			103984
003			DE-He213
005			20230102113154.0
007			cr nn 008mamaa
008			141008s2015 gw | s |||| 0|eng d
020			_a9783319068381
024	7		_a10.1007/978-3-319-06838-1 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC
050		4	_aTK7895.G36 2015 EB
100	1		_aGong, Lingkan _eautor _9669768
245	1	0	_aFunctional Verification of Dynamically Reconfigurable FPGA-based Systems _cby Lingkan Gong, Oliver Diessel.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XXI, 216 páginas 72 ilustraciones, 48 ilustraciones a color.)
505	0		_aIntroduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References.
520	3		_aThis book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc. ...).
650		7	_aDispositivos FPGAs _2embne _9667973
700	1		_aDiessel, Oliver _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2010112950 _1http://viaf.org/viaf/137620321/
776	0	8	_iEdición impresa: _z9783319068374
776	0	8	_iEdición impresa: _z9783319068398
776	0	8	_iEdición impresa: _z9783319380865
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-06838-1 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
490	0		_aEngineering (Springer-11647)
988			_aEBSPRINGER_2018
998			_b06/2019 _dz _ek _feng _ggw _h0
999			_c103984 _d103984 _x1