000			04664nam a22004455i 4500
999			_c103878 _d103878 _x1
001			103878
003			DE-He213
005			20230102113150.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			140823s2015 gw | s |||| 0|eng d
020			_a9783319071398
024	7		_a10.1007/978-3-319-07139-8 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7885.7 _b2015 EB
100	1		_aCerny, Eduard. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/nb97074909 _1http://viaf.org/viaf/271538942/
245	1	0	_aSVA: The Power of Assertions in SystemVerilog _cby Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny.
250			_a2nd edition
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XIX, 590 páginas 173 ilustraciones)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aPart I. Opening -- Introduction -- System Verilog Language and Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference.- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences.- Clocks -- Resets -- Procedural Concurrent Assertions.- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers -- Checkers in Formal Verification.- Checker Libraries -- Appendix -- References.- Index.
520	3		_aThis book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA).  It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis.  The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties.  The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components.  The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play.  This second edition covers the features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers.  With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.  ·         Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA); ·         Includes step-by-step examples of how SVA can be used to construct powerful  and reusable sets of properties; ·         Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard.
988			_aEBSPRINGER_2018
650		7	_2embne _9668846 _aVERILOG (Lenguaje de descripción del soporte físico)
650		7	_2embne _aVHDL (Lenguaje de descripción del soporte físico) _9160754
650		7	_2embne _9150789 _aLenguajes de descripción del soporte físico
700	1		_aDudani, Surrendra. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/219761387/
700	1		_aHavlicek, John. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/113677024/ _1http://dbpedia.org/resource/John_Havlicek
700	1		_aKorchemny, Dmitry. _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iEdición impresa: _z9783319071381
776	0	8	_iEdición impresa: _z9783319071404
776	0	8	_iEdición impresa: _z9783319331096
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-07139-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2019 _dz _ejf _zSI