000			03074nam a22003975i 4500
999			_c103841 _d103841 _x1
001			103841
003			DE-He213
005			20230102113148.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			141108s2015 xxu| s |||| 0|eng d
020			_a9781461440789
024	7		_a10.1007/978-1-4614-4078-9 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7874 _b2015 EB
245	1	0	_aCircuit Design for Reliability _cedited by Ricardo Reis, Yu Cao, Gilson Wirth.
264		1	_aNew York, NY _bSpringer International Publishing _c2015
300			_a1 recurso en línea (VI, 272 páginas 190 ilustraciones, 132 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Recent Trends in Bias Temperature Instability -- Charge trapping phenomena in MOSFETS: From Noise to Bias Temperature Instability -- Atomistic Simulations on Reliability -- On-chip characterization of statistical device degradation -- Circuit Resilience Roadmap -- Layout Aware Electromigration Analysis of Power/Ground Networks -- Power-Gating for Leakage Control and Beyond -- Soft Error Rate and Fault Tolerance Techniques for FPGAs.
520	3		_aThis book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.
988			_aEBSPRINGER_2018
650		7	_aCircuitos integrados _2embne _9139614
700	1		_aReis, Ricardo _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _0http://id.loc.gov/authorities/names/nr2002001811 _1http://viaf.org/viaf/126144814444407525004/ _9100026
700	1		_aCao, Yu. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _0http://id.loc.gov/authorities/names/n2004059159 _1http://viaf.org/viaf/4964097/
700	1		_aWirth, Gilson. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _0http://id.loc.gov/authorities/names/nb2013027627 _1http://viaf.org/viaf/305833352/
776	0	8	_iEdición impresa: _z9781461440796
776	0	8	_iEdición impresa: _z9781461440772
776	0	8	_iEdición impresa: _z9781493941568
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-1-4614-4078-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2019 _dz _eIG _zSI