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007			cr nn 008mamaa
008			141107s2015 xxu| s |||| 0|eng d
020			_a9781461408215
024	7		_a10.1007/978-1-4614-0821-5 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7874.53 _b2015 EB
100	1		_aMoiseev, Konstantin. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/57767094/
245	1	0	_aMulti-Net Optimization of VLSI Interconnect _cby Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
264		1	_aNew York, NY _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XVI, 233 páginas 124 ilustraciones, 44 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aAn Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
520	3		_aThis book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips. This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies.  The Authors of this book didn't only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them. --Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect. --Eby G. Friedman, Distinguished Professor, University of Rochester.
988			_aEBSPRINGER_2018
650		7	_aCircuitos integrados _2embne _9139614
650		7	_9668336 _aInterconexión de redes (Telecomunicaciones)
700	1		_aKolodny, Avinoam. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/32149841966302841981/
700	1		_aWimer, Shmuel. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iEdición impresa: _z9781461408222
776	0	8	_iEdición impresa: _z9781461408208
776	0	8	_iEdición impresa: _z9781493942626
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-1-4614-0821-5 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2019 _dz _eIG _zSI