000			03038nam a22003735i 4500
999			_c103815 _d103815 _x1
001			103815
003			DE-He213
005			20230102113147.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			150612s2015 xxu| s |||| 0|eng d
020			_a9781461413233
024	7		_a10.1007/978-1-4614-1323-3 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7874.53 _b2015 EB
100	1		_aSaini, Sandeep. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aLow Power Interconnect Design _cby Sandeep Saini.
264		1	_aNew York, NY _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XVII, 152 páginas 111 ilustraciones, 12 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aPart I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
520	3		_aThis book provides practical solutions for delay and power reduction for on-chip interconnects and buses.  It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.  Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.   ·         Provides practical solutions for delay and power reduction for on-chip interconnects and buses; ·         Focuses on Deep Sub micron technology devices and interconnects; ·         Offers in depth analysis of delay, including details regarding crosstalk and parasitics;  ·         Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; ·         Provides detailed simulation results to support the theoretical discussions. ·         Provides details of delay and power efficient bus coding techniques.
988			_aEBSPRINGER_2018
650		7	_9668336 _aInterconexión de redes (Telecomunicaciones)
776	0	8	_iEdición impresa: _z9781461413226
776	0	8	_iEdición impresa: _z9781461413240
776	0	8	_iEdición impresa: _z9781493942947
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-1-4614-1323-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b04/2019 _dz _eIG _zSI