000			03485nam a22003855i 4500
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007			cr nn 008mamaa
008			141030s2015 gw | s |||| 0|eng d
020			_a9783319105697
024	7		_a10.1007/978-3-319-10569-7 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK5102.96 _bA383 2015 EB
245	1	0	_aAdvanced Hardware Design for Error Correcting Codes _cedited by Cyrille Chavet, Philippe Coussy.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (IX, 192 páginas 81 ilustraciones, 25 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aUser Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.                                                                                                                                       .
520	3		_aThis book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
988			_aEBSPRINGER_2018
650		7	_aCodificación, Teoría de la _2embne _9666753
700	1		_aChavet, Cyrille. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _1http://viaf.org/viaf/197239946/
700	1		_aCoussy, Philippe. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _0http://id.loc.gov/authorities/names/n2009008382 _1http://viaf.org/viaf/78845621/
776	0	8	_iEdición impresa: _z9783319105680
776	0	8	_iEdición impresa: _z9783319105703
776	0	8	_iEdición impresa: _z9783319355108
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-10569-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2019 _dz _eIG _zSI