000			03384nam a22003855i 4500
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005			20230102113140.0
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007			cr nn 008mamaa
008			140925s2015 gw | s |||| 0|eng d
020			_a9783319093093
024	7		_a10.1007/978-3-319-09309-3 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7874.75 _bD443 2015 EB
100	1		_aDehbashi, Mehdi. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/5893150033046211180005/
245	1	0	_aDebug Automation from Pre-Silicon to Post-Silicon _cby Mehdi Dehbashi, Görschwin Fey.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XIV, 171 páginas 93 ilustraciones, 55 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Preliminaries -- Part I Debug of Design Bugs -- Automated Debugging for Logic Bugs -- Automated Debugging from Pre-Silicon to Post-Silicon -- Automated Debugging for Synchronization Bugs -- Part II Debug of Delay Faults -- Analyzing Timing Variations -- Automated Debugging for Timing Variations -- Efficient Automated Speedpath Debugging -- Part III Debug of Transactions -- Online Debug for NoC-Based Multiprocessor SoCs -- Summary and Outlook.
520	3		_aThis book describes automated debugging approaches for the bugs and the faults which appear in different abstraction levels of a hardware system. The authors employ a transaction-based debug approach to systems at the transaction-level, asserting the correct relation of transactions. The automated debug approach for design bugs finds the potential fault candidates at RTL and gate-level of a circuit. Debug techniques for logic bugs and synchronization bugs are demonstrated, enabling readers to localize the most difficult bugs. Debug automation for electrical faults (delay faults)finds the potentially failing speedpaths in a circuit at gate-level. The various debug approaches described achieve high diagnosis accuracy and reduce the debugging time, shortening the IC development cycle and increasing the productivity of designers. Describes a unified framework for debug automation used at both pre-silicon and post-silicon stages; Provides approaches for debug automation of a hardware system at different levels of abstraction, i.e., chip, gate-level, RTL and transaction level; Includes techniques for debug automation of design bugs and electrical faults, as well as an infrastructure to debug NoC-based multiprocessor SoCs.
988			_aEBSPRINGER_2018
650		7	_aCircuitos integrados _xDiseño y construcción _2embne _9179611
700	1		_aFey, Görschwin. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2005109143 _1http://viaf.org/viaf/26806068/
776	0	8	_iEdición impresa: _z9783319093086
776	0	8	_iEdición impresa: _z9783319093109
776	0	8	_iEdición impresa: _z9783319356105
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-09309-3 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2019 _dz _eIG _zSI