000			03266nam a22003975i 4500
999			_c103497 _d103497 _x1
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007			cr nn 008mamaa
008			151216s2015 gw | s |||| 0|eng d
020			_a9783319257662
024	7		_a10.1007/978-3-319-25766-2 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7888.4 _b2015 EB
100	1		_aEzz-Eldin, Rabab. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aAnalysis and Design of Networks-on-Chip Under High Process Variation _cby Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XXI, 141 páginas 84 ilustraciones, 34 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.
520	3		_aThis book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies;  Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion.
988			_aEBSPRINGER_2018
650		7	_aCircuitos lógicos _2embne _9139135
700	1		_aEl-Moursy, Magdy Ali. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aHamed, Hesham F. A. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iEdición impresa: _z9783319257648
776	0	8	_iEdición impresa: _z9783319257655
776	0	8	_iEdición impresa: _z9783319798370
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-25766-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2019 _dz _eIG _zSI