000			03996nam a22003975i 4500
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008			141014s2015 gw | s |||| 0|eng d
020			_a9783319019970
024	7		_a10.1007/978-3-319-01997-0 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7871.99.M44 _b2015 EB
100	1		_aAlioto, Massimo. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/nb2004310685 _1http://viaf.org/viaf/243553055/
245	1	0	_aFlip-Flop Design in Nanometer CMOS _bFrom High Speed to Low Energy _cby Massimo Alioto, Elio Consoli, Gaetano Palumbo.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XV, 260 páginas 123 ilustraciones, 5 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aThe Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.
520	3		_aThis book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate  and postgraduate students (already familiar with digital circuits and timing). • Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems • Offers in-depth analysis of the impact of nanometer effects on  design tradeoffs • Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits • Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop  .
988			_aEBSPRINGER_2018
650		7	_aCircuitos integrados CMOS _2embne _9160755
700	1		_aConsoli, Elio. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/311759270/
700	1		_aPalumbo, Gaetano. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/n93902541 _1http://viaf.org/viaf/90153499/
776	0	8	_iEdición impresa: _z9783319019987
776	0	8	_iEdición impresa: _z9783319019963
776	0	8	_iEdición impresa: _z9783319345925
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-01997-0 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2019 _dz _eIG _zSI