000			03202nam a22003855i 4500
999			_c103416 _d103416 _x1
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003			DE-He213
005			20230102113129.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			150519s2015 gw | s |||| 0|eng d
020			_a9783319179247
024	7		_a10.1007/978-3-319-17924-7 _2doi
040			_bspa _dES-MaUEC
050		4	_aTK7895.G36 _b2015 EB
100	1		_aSimpson, Philip Andrew. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aFPGA Design _bBest Practices for Team-based Reuse _cby Philip Andrew Simpson.
250			_a2nd edition
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XI, 257 páginas 129 ilustraciones, 85 ilustraciones a color.)
336			_2rdacontent _aTexto (visual) _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Project Management -- Design Specification -- System Modeling -- Resource Scoping -- Design Environment -- Board Design -- Power and Thermal analysis -- Team Based Design -- RTL Design -- IP reuse -- Embedded Design -- Functional verification -- Timing Closure -- High level  Design -- In System Debug -- Design Sign-off.
520	3		_aThis book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expanded to include more up to date techniques as well as providing more extensive scripts and RTL code that can be reused by readers. Presents complete, field-tested methodology for FPGA design, focused on reuse across design teams; Offers best practices for FPGA timing closure, in-system debug, and board design; Details techniques to resolve common pitfalls in designing with FPGAs.
988			_aEBSPRINGER_2018
650		7	_aDispositivos FPGAs _2embne _9667973
776	0	8	_iEdición impresa: _z9783319179254
776	0	8	_iEdición impresa: _z9783319179230
776	0	8	_iEdición impresa: _z9783319342481
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-17924-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b03/2019 _dz _eIG _zSI