000			03304nam a22003255i 4500
001			103406
003			DE-He213
005			20230102113129.0
007			cr nn 008mamaa
008			141212s2015 gw | s |||| 0|eng d
020			_a9783319123707
024	7		_a10.1007/978-3-319-12370-7 _2doi
040			_aES-MaUEC _bspa
050		4	_aQA76.9.A25 _bR434 2015 EB
100	1		_aRebeiro, Chester _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2015029407 _1http://viaf.org/viaf/314911170/
245	1	0	_aTiming Channels in Cryptography _bA Micro-Architectural Perspective _cby Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya.
264		1	_aCham _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XVII, 152 páginas 75 ilustraciones, 14 ilustraciones a color)
505	0		_aAn Introduction to Timing Attacks -- Modern Cryptography -- Superscalar Processors, Cache Memories, and Branch Predictors -- Time-Driven Cache Attacks -- Advanced Time-Driven Cache Attacks on Block Ciphers -- A Formal Analysis of Time-Driven Cache Attacks -- Profiled Time-Driven Cache Attacks on Block Ciphers -- Access-Driven Cache Attacks on Block Ciphers -- Branch Prediction Attacks -- Countermeasures for Timing Attacks.
520	3		_aThis book deals with timing attacks on software implementations of encryption algorithms. It describes and analyzes various unintended covert timing channels that are formed when ciphers are executed in microprocessors. Modern superscalar microprocessors are considered, which are enabled with features such as multi-threaded, pipelined, parallel, speculative, and out-of-order execution. Various timing attack algorithms are described and analyzed for  block ciphers as well as public-key ciphers. The interplay between the cipher implementation, system architecture, and the attack's success is analyzed. Further hardware and software countermeasures are discussed with the aim of illustrating methods to build systems that can protect against these attacks. Discusses various timing attack algorithms in detail allowing readers to reconstruct the attack. Provides several experimental results to support the theoretical analysis provided in the book. Analyzes information leakage from cache memories and branch prediction units in the processor. Examines information leakage models that would help quantify leakage in a covert timing channels.
650		7	_aCriptografía (Informática) _2embne _9158201
700	1		_aMukhopadhyay, Debdeep _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/nb2011029582 _1http://viaf.org/viaf/214785601/
700	1		_aBhattacharya, Sarani _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2015029553 _1http://viaf.org/viaf/314911289/
776	0	8	_iEdición impresa: _z9783319123691
776	0	8	_iEdición impresa: _z9783319123714
776	0	8	_iEdición impresa: _z9783319380773
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-12370-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
490	0		_aEngineering (Springer-11647)
998			_b03/2019 _dz _ek _feng _ggw _h0
999			_c103406 _d103406 _x1