000			03423nam a22003255i 4500
001			103245
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005			20230102113121.0
007			cr nn 008mamaa
008			140827s2015 xxu| s |||| 0|eng d
020			_a9781461443018
024	7		_a10.1007/978-1-4614-4301-8 _2doi
050		4	_aTK7888.4 _b.D565 2015 EB
040			_aES-MaUEC _bspa
100	1		_aDimitrakopoulos, Giorgos _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/24146030668235862987/
245	1	0	_aMicroarchitecture of Network-on-Chip Routers _bA Designer's Perspective _cby Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
264		1	_aNew York, NY _bSpringer International Publishing _c2015
300			_a1 recurso en línea (XIV, 175 páginas 134 ilustraciones, 77 ilustraciones a color.)
505	0		_aIntroduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.
520	3		_aThis book focuses on the microarchitecture of network-on-chip routers from a designer's perspective, providing ready-to-use solutions for simple and more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail. The authors provide numerous detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner, beginning from basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions.  · Covers all aspects of the microarchitecture of Network-on-Chip routers; · Justifies and explains every design choice that is presented in a ready-to-use manner following a designer's perspective; · Describes performance-enhancing features in a step-by-step manner; ·Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
650		7	_aCircuitos lógicos _2embne _9139135
700	1		_aPsarras, Anastasios _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aSeitanidis, Ioannis _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/18150868296322072503/
776	0	8	_iEdición impresa: _z9781461443025
776	0	8	_iEdición impresa: _z9781461443001
776	0	8	_iEdición impresa: _z9781493945580
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-1-4614-4301-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
490	0		_aEngineering (Springer-11647)
998			_b03/2019 _dz _ef _feng _ggw _h0
999			_c103245 _d103245 _x1