000			03773nam a22003735i 4500
001			102875
003			DE-He213
005			20230102113103.0
007			cr nn 008mamaa
008			180314s2018 gw | s |||| 0|eng d
020			_a9783319743820
024	7		_a10.1007/978-3-319-74382-0 _2doi
040			_aES-MaUEC _bspa
050		4	_aTK7888.4 2018 EB
100	1		_aBuccella, Pietro _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/67146573734738100427/
245	1	0	_aParasitic Substrate Coupling in High Voltage Integrated Circuits _bMinority and Majority Carriers Propagation in Semiconductor Substrate _cby Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese.
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XVII, 183 páginas 124 ilustraciones, 73 ilustraciones a color)
347			_atext file _bPDF
490	0		_aAnalog Circuits and Signal Processing _x1872-082X
505	0		_aChapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.
520	3		_aThis book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections.
650		7	_aCircuitos lógicos _2embne _9139135
650		7	_aElectrónica _2embne _9138690
700	1		_aStefanucci, Camillo _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/817145857913723021282/
700	1		_aKayal, Maher _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/nb2005020390 _1http://viaf.org/viaf/38895615/
700	1		_aSallese, Jean-Michel _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/n2018005201 _1http://viaf.org/viaf/1057145857143022922975/
776	0	8	_iEdición impresa: _z9783319743813
776	0	8	_iEdición impresa: _z9783319743837
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-74382-0 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
490	0		_aEngineering (Springer-11647)
988			_aEBSPRINGER_2018
998			_b02/2019 _dz _ek _feng _ggw _h0
999			_c102875 _d102875 _x1