000			03052nam a22003855i 4500
999			_c102812 _d102812
001			102812
003			DE-He213
005			20230102113100.0
006			a||||fo|||| 00| 0
007			cr nn 008mamaa
008			171005s2018 gw | s |||| 0|eng d
020			_a9783319666198
024	7		_a10.1007/978-3-319-66619-8 _2doi
040			_bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874.66 _bK466 2018 EB
100	1		_aKhondkar, Progyna. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aLow-Power Design and Power-Aware Verification _cby Progyna Khondkar.
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XV, 155 páginas 19 ilustraciones, 12 ilustraciones a color.)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_a1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .
520	3		_aUntil now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .
988			_aEBSPRINGER_2018
650		7	_2embne _9139614 _aCircuitos integrados
776	0	8	_iEdición impresa: _z9783319666181
776	0	8	_iEdición impresa: _z9783319666204
776	0	8	_iEdición impresa: _z9783319882864
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-66619-8 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE