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008			170628s2018 gw | s |||| 0|eng d
020			_a9783319594187
024	7		_a10.1007/978-3-319-59418-7 _2doi
040			_bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7888.4 _bM448 2018 EB
100	1		_aMehta, Ashok B. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2014151279 _1http://viaf.org/viaf/311778896/ _998903
245	1	0	_aASIC/SoC Functional Design Verification _bA Comprehensive Guide to Technologies and Methodologies _cby Ashok B. Mehta.
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XXXI, 328 páginas 175 ilustraciones, 160 ilustraciones a color.)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aChapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
520	3		_aThis book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
988			_aEBSPRINGER_2018
650		7	_2embne _9139610 _aCircuitos electrónicos
776	0	8	_iEdición impresa: _z9783319594170
776	0	8	_iEdición impresa: _z9783319594194
776	0	8	_iEdición impresa: _z9783319866208
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-59418-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE