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710	2		_aSpringerLink (Online service) _0http://id.loc.gov/authorities/names/no2005046756 _1http://viaf.org/viaf/274647764/ _9106996
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020			_a9789811072512
024	7		_a10.1007/978-981-10-7251-2 _2doi
040			_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7874.75 _b2018 EB
245	0	0	_aVLSI Design: Circuits, Systems and Applications : _bSelect Proceedings of ICNETS2, Volume V _cedited by Jie Li, A Ravi Sankar, P Augusta Sophy Beulet.
264		1	_aSingapore _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XIV, 270 páginas) _b229 ilustraciones, 114 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aLecture Notes in Electrical Engineering _x1876-1100 _v469
490	0		_aEngineering (Springer-11647)
505	0		_aFront-End CMOS Circuit for Low Power Consumption -- A Preliminary Study of Oscillators, Phase and Frequency Detector and Charge Pump for Phase Locked Loop (PLL) Applications -- All Digital RF Transmitter with Highly Power Efficient Doherty Power Amplifier -- Adiabatic Techniques for Energy Efficient Barrel Shifter Design -- A 79Ghz CMOS LNA with Adaptive Biasing -- X-Band Phased-Array Transmitter in 180nm Sige Bicmos Technology with Stacked Power Amplifier -- Short Range Low Data Rate Pulsed UWB Transmitter -- A New High Speed Multiplier Based on Carry Look Ahead Adder and Compressor -- Real-Time Automatic Peaks and Onsets Detection of Photoplethysmographic Signals -- Survey on Design of Low Power CMOS Four Quadrant Analog Multiplier in Nano-Meter Scaling -- Designing 5t Embedded Dram Cell for Ultra Low Power Low Voltage Applications Based on Schmitt Trigger -- Design and Implementation of Multi-Bit Self-Checking Carry-Select Adder -- A Novel Adiabatic Logic for Low Power VLSI Circuit Design and Power Optimization Using Finfet -- Test Signal Generation for Detecting Faults On Mil-Std 1553 Bus -- Design of Ultra Low Voltage- Energy Efficient Hybrid Full Adder Circuit -- Mtcmos Based Soft Start Circuit for Low Leakage Led Driver with Minimum In-Rush Current -- Implementation of Dual-Hysteresis Mode Flip-Flop Multivibrator    Using Differential Voltage Current Conveyor -- High Performance Domino Logic Circuit Design By Contention Reduction -- Differential Power Analysis (Dpa) Resistant Cryptographic S-Box -- Implementation of Radix-2 Butterfly Using Distributed Arithmatic Algorithm (Daa) -- An Area Efficient Design of Warped Filters -- Design of Arithmetic and Logical Unit (Alu) Using Subthreshold Adiabatic Logic for Low Power Application -- Design of Sample and Hold for High Speed Analog To Digital Converter -- Fpga Masked S-Box Implementation for Aes Engine -- Pipelined and Parallel Architecture of Reversible Watermarking for Grayscale Images -- Design and Verification of Amba Axi3 Protocol -- Design of Multi-Stage Cmos Ota for Low-Power and High Driving Capability.
520	3		_aThis book gathers a collection of papers by international experts presented at the International Conference on NextGen Electronic Technologies (ICNETS2-2017), which cover key developments in the field of electronics and communication engineering. ICNETS2 encompassed six symposia covering all aspects of the electronics and communications domains, including relevant nano/micro materials and devices. This book showcases the latest research in very-large-scale integration (VLSI) Design: Circuits, Systems and Applications, making it a valuable resource for all researchers, professionals, and students working in the core areas of electronics and their applications, especially in digital and analog VLSI circuits and systems.
988			_aEBSPRINGER_2018
650		7	_2embne _aCircuitos integrados _vCongresos y asambleas _9139614
700	1		_aLi, Jie _0http://id.loc.gov/authorities/names/n84015645 _1http://viaf.org/viaf/4957151/ _9671940
700	1		_aSankar, A Ravi. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt _1http://viaf.org/viaf/84975629/ _1http://dbpedia.org/resource/Ravi_Shankar
700	1		_aBeulet, P Augusta Sophy. _eeditor literario _4edt _4http://id.loc.gov/vocabulary/relators/edt
776	0	8	_iEdición impresa: _z9789811072505
776	0	8	_iEdición impresa: _z9789811072529
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-981-10-7251-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE
998			_b05/2020 _dz _ek _zSI