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008			170706s2018 gw | s |||| 0|eng d
020			_a9783319604022
024	7		_a10.1007/978-3-319-60402-2 _2doi
040			_bspa _cES-MaUEC _dES-MaUEC
050		4	_aTK7895.E42 _bM456 2018 EB
100	1		_aMeinerzhagen, Pascal. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/146147724950264592625/
245	1	0	_aGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip _cby Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish.
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (IX, 146 páginas 84 ilustraciones a color.)
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aMotivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions.
520	3		_aThis book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
988			_aEBSPRINGER_2018
650		7	_2embne _9161392 _aSistemas informáticos
700	1		_aTeman, Adam. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/308282789/
700	1		_aGiterman, Robert. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aEdri, Noa. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
700	1		_aBurg, Andreas. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/13170408/
700	1		_aFish, Alexander. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/60510434/
776	0	8	_iEdición impresa: _z9783319604015
776	0	8	_iEdición impresa: _z9783319604039
776	0	8	_iEdición impresa: _z9783319868554
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-60402-2 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE