000			03401nam a22004091i 4500
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003			ES-MaUEC
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008			180419s2018 gw | o |||| 0|eng d
020			_a9783319790817
024	7		_a10.1007/978-3-319-79081-7 _2doi
040			_bspa _cES-MaUEC _dES-MaUEC
041	0		_aeng
050		4	_aQA76.9.A25 _b2018 EB
100	1		_aSalmani, Hassan _eautor _9673278
245	1	0	_aTrusted Digital Circuits : _bHardware Trojan Vulnerabilities, Prevention and Detection _cby Hassan Salmani
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XI, 131 páginas) _b76 ilustraciones, 43 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aEngineering (Springer-11647)
505	0		_aThe Global Integrated Circuit Supply Chain Flow and the Hardware Trojan Attack -- Circuit Vulnerabilities to Hardware Trojans at the Register Transfer Level -- Design Techniques for Hardware Trojans Prevention and Detection at the Register Transfer Level -- Circuit Vulnerabilities to Hardware Trojans at the Gate Level -- Design Techniques for Hardware Trojans Prevention and Detection at the Gate Level -- Circuit Vulnerabilities to Hardware Trojan at the Layout Level -- Design Techniques for Hardware Trojans Prevention and Detection at the Layout Level -- Trusted Testing Techniques for Hardware Trojan Detection -- Hardware Trojans in Analog and Mixed-Signal Integrated Circuits.
520	3		_aThis book describes the integrated circuit supply chain flow and discusses security issues across the flow, which can undermine the trustworthiness of final design. The author discusses and analyzes the complexity of the flow, along with vulnerabilities of digital circuits to malicious modifications (i.e. hardware Trojans) at the register-transfer level, gate level and layout level. Various metrics are discussed to quantify circuit vulnerabilities to hardware Trojans at different levels. Readers are introduced to design techniques for preventing hardware Trojan insertion and to facilitate hardware Trojan detection. Trusted testing is also discussed, enabling design trustworthiness at different steps of the integrated circuit design flow. Coverage also includes hardware Trojans in mixed-signal circuits. Provides a comprehensive vulnerability analysis across the integrated circuits design flow; Introduces security metrics to measure quantitatively the vulnerability of a circuit to hardware Trojan insertion; Describes design techniques to prevent hardware Trojan insertion and to facilitate hardware Trojan detection; Presents testing techniques for trustworthiness at each circuit level.
988			_aEBSPRINGER_2018
650		7	_2embne _aSeguridad informática _9158200
650		7	_2embne _aProceso de datos _9141180
650		7	_2embne _aInformática _9139268
776	0	8	_iEdición impresa: _z9783319790800
776	0	8	_iEdición impresa: _z9783319790824
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-79081-7 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b04/2020 _dz _eb _zSI