000			02848nam a22004331i 4500
999			_c102231 _d102231 _x1
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003			ES-MaUEC
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007			cr nn 008mamaa
008			180418s2018 gw | o |||| 0|eng d
020			_a9783319754659
024	7		_a10.1007/978-3-319-75465-9 _2doi
040			_bspa _cES-MaUEC _dES-MaUEC
041	0		_aeng
050		4	_a TK7874.84 _b2018 EB
100	1		_aChampac, Victor _eautor _9673275
245	1	0	_aTiming Performance of Nanometer Digital Circuits Under Process Variations _cby Victor Champac, Jose Garcia Gervacio
264		1	_aCham _bSpringer International Publishing _c2018
300			_a1 recurso en línea (XVIII, 185 páginas) _b116 ilustraciones, 91 ilustraciones a color
336			_2rdacontent _aTexto _btxt
337			_2rdamedia _aelectrónico _bc
338			_2rdacarrier _arecurso electrónico _bcr
347			_atext file _bPDF
490	0		_aFrontiers in Electronic Testing, _x0929-1296 _v39
490	0		_aEngineering (Springer-11647)
505	0		_aIntroduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.
520	3		_aThis book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
988			_aEBSPRINGER_2018
650		7	_2embne _aNanotecnología _9158453
650		7	_2embne _aCircuitos integrados _9139614
650		7	_2embne _aElectrónica _9138690
700	1		_aGarcia Gervacio, Jose. _eautor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
776	0	8	_iEdición impresa: _z9783319754642
776	0	8	_iEdición impresa: _z9783319754666
856	4	0	_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-75465-9 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid)
942			_2lcc _cLE _n0
998			_b04/2020 _dz _eb _zSI