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| 003 | DE-He213 | ||
| 005 | 20230102113022.0 | ||
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| 007 | cr nn 008mamaa | ||
| 008 | 170624s2018 gw | s |||| 0|eng d | ||
| 020 | _a9783319598376 | ||
| 024 | 7 |
_a10.1007/978-3-319-59837-6 _2doi |
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| 040 |
_aES-MaUEC _bspa _cES-MaUEC _dES-MaUEC |
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| 050 |
_aQA267.5.S4 _bB375 2018 EB |
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| 100 | 1 |
_aBarkalov, Alexander _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2009024436 _1http://viaf.org/viaf/78969994/ _997645 |
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| 245 | 1 | 0 |
_aLogic Synthesis for Finite State Machines Based on Linear Chains of States _bFoundations, Recent Developments and Challenges _cby Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski. |
| 264 | 1 |
_aCham _bSpringer International Publishing _c2018 |
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| 300 | _a1 recurso en línea (VIII, 225 páginas 145 ilustraciones) | ||
| 336 |
_2rdacontent _aTexto _btxt |
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| 337 |
_2rdamedia _aelectrónico _bc |
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| 338 |
_2rdacarrier _arecurso electrónico _bcr |
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| 347 |
_atext file _bPDF |
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| 490 | 0 |
_aStudies in Systems, Decision and Control _x2198-4182 _v113 |
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| 490 | 0 | _aEngineering (Springer-11647) | |
| 505 | 0 | _aIntroduction -- Finite state machines and field-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs. | |
| 520 | 3 | _aThis book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units. | |
| 988 | _aEBSPRINGER_2018 | ||
| 650 | 7 |
_aIngeniería de sistemas _2embne _9138451 |
|
| 700 | 1 |
_aTitarenko, Larysa _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _0http://id.loc.gov/authorities/names/no2009047498 _1http://viaf.org/viaf/80528830/ _997646 |
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| 700 | 1 |
_aBieganowski, Jacek _eautor _4aut _4http://id.loc.gov/vocabulary/relators/aut _1http://viaf.org/viaf/250533804/ |
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| 776 | 0 | 8 |
_iEdición impresa: _z9783319598369 |
| 776 | 0 | 8 |
_iEdición impresa: _z9783319598383 |
| 776 | 0 | 8 |
_iEdición impresa: _z9783319867144 |
| 856 | 4 | 0 |
_uhttps://go.openathens.net/redirector/universidadeuropea.es?url=https://doi.org/10.1007/978-3-319-59837-6 _zAcceso a este recurso digital (usuarios Universidad Europea de Madrid) |
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_2lcc _cLE |
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| 998 |
_b12/2018 _dz _ef _feng _ggw _h0 |
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