Biblioteca CRAI Dulce Chacón - Universidad Europea de Madrid

CRAI Library - Madrid
Your cart is empty.
My folder ( items) | My account

Your search returned 8 results.

Sort
Unhighlight Highlight
Select all Clear all
Select titles to:
Results
Digital logic design using verilog : coding and RTL synthesis / by Vaibbhav Taraate

by Taraate, Vaibbhav | SpringerLink (Online service).

Material type: bookE-book Publisher: New Delhi : Springer, 2016
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7868 .L6 T37 2016 EB reference

Add to cart
PLD based design with VHDL : RTL design, synthesis and implementation / Vaibbhav Taraate.

by Taraate, Vaibbhav.

Material type: bookE-book Publisher: Singapore : Springer, 2017
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7874.6 T373 2017 EB reference

Add to cart
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / by Vaibbhav Taraate.

by SpringerLink (Online service) | Taraate, Vaibbhav, autor.

Material type: bookE-book Publisher: Singapore : Imprint: Springer, 2019
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7895.E42 2019 EB reference

Add to cart
Logic Synthesis and SOC Prototyping : RTL Design using VHDL / by Vaibbhav Taraate.

by SpringerLink (Online service) | Taraate, Vaibbhav, autor.

Edition: First editionSource: Springer eBooksMaterial type: bookE-book Publisher: Singapore : Springer Singapore : Imprint Springer, 2020
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7895.E42 2020 EB reference

Add to cart
SystemVerilog for Hardware Description RTL Design and Verification / by Vaibbhav Taraate

by Taraate, Vaibbhav, autor | SpringerLink (Online service).

Edition: First editionMaterial type: bookE-book Publisher: Singapore : Springer Singapore : Imprint: Springer, 2020
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7885.7 2020 EB reference

Add to cart
ASIC Design and Synthesis : RTL Design Using Verilog / by Vaibbhav Taraate.

by Taraate, Vaibbhav, autor.

Edition: First edition 2021Material type: bookE-book Publisher: Singapore : Springer International Publishing, 2021
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7888.4 2021 EB reference

Add to cart
Digital Logic Design Using Verilog : Coding and RTL Synthesis / by Vaibbhav Taraate

by Taraate, Vaibbhav, autor.

Edition: 2nd edition 2022Material type: bookE-book Publisher: Singapore : Springer International Publishing, 2022
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7868 .L6 2022 EB reference

Add to cart
Digital Design Techniques and Exercises : A Practice Book for Digital Logic Design / by Vaibbhav Taraate

by Taraate, Vaibbhav, autor.

Edition: 1st edition 2022Material type: bookE-book Publisher: Singapore : Springer International Publishing, 2022
Online access: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Items
Location Call no. Status Vol info Loan type
Acceso Electrónico (UEM) TK7868.L6 2022 EB reference

Add to cart
Pages