6.4.1 WCDMA Cell Search.

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Preface; Acknowledgements; Contents; Contributors; 1 The Evolution of Software-Defined Radio: An Introduction; Part-I: Architectures, Designs, and Implementations; Part-II: Software-Based Radio Cognition and Implementation Tools; Reference; Part I Architectures, Designs and Implementations; 2 Design Transformation from a Single-Core to a Multi-Core Architecture Targeting Massively Parallel Signal Processing Algorithms; 2.1 Introduction; 2.2 Existing State of the Art; 2.2.1 MORPHEUS; 2.2.2 P2012; 2.2.3 NineSilica; 2.2.4 RAW; 2.2.5 CRISP; 2.2.6 Intel's Single-Chip Cloud Computer; 2.2.7 TILE64™

2.3 Scalable CGRAs2.4 The Network-on-Chip; 2.5 Hardware/Software Integration; 2.5.1 Loading Configuration and Data; 2.5.2 Context Enabling and Execution; 2.5.3 Synchronization; 2.6 Heterogeneous Accelerator-Rich Reconfigurable Platform; 2.7 Application Mapping; 2.8 Measurement and Estimation; 2.9 Evaluation and Comparisons; 2.10 Conclusions; References; 3 The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio; 3.1 Introduction; 3.2 Related Work; 3.3 The CoreVA-MPSoC Architecture; 3.3.1 CoreVA VLIW CPU; 3.3.2 CPU Cluster; 3.3.3 Network-on-Chip; 3.3.3.1 Switch Box.

3.3.3.2 Network Interface3.3.3.3 Globally Asynchronous Locally Synchronous; 3.4 Implementation Results in a 28nm FD-SOI Technology; 3.4.1 CoreVA VLIW CPU Implementation Results; 3.4.2 MPSoC Implementation Results; 3.5 Programming the CoreVA-MPSoC; 3.5.1 Communication Model; 3.5.2 StreamIt Language and Compiler; 3.6 Mapping SDR Algorithms to the CoreVA-MPSoC; 3.6.1 Mapping SDR Algorithms to a Single CPU VLIW Core; 3.6.2 Benchmark Results for CoreVA-MPSoC; 3.7 Summary; References; 4 Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array.

4.1 Introduction4.2 Platform Architecture; 4.3 Design Implementation and Algorithm Mapping; 4.3.1 Time Synchronization; 4.3.2 Frequency Offset Estimation; 4.3.3 Channel Estimation; 4.4 Experimental Results and Conclusion; References; 5 Reconfigurable Multiprocessor Systems-on-Chip; 5.1 Introduction and Motivation; 5.2 Background: Reconfigurable Hardware; 5.3 Dynamic and Partial Reconfiguration; 5.3.1 Benefits of Dynamic and Partial Reconfiguration for Software Defined Radio Applications; 5.4 Reconfigurable Multiprocessor Systems-on-Chip.

5.4.1 rMIMD: Multiprocessors with Reconfigurable Instruction Streams5.4.2 MIrMD: Multiprocessors with Reconfigurable Data Streams; 5.4.3 rMIrMD: Multiprocessors with Reconfigurable Instruction and Reconfigurable Data Streams; 5.4.3.1 RAMPSoC; 5.4.3.2 RAR-MPSoC; 5.5 Conclusion and Outlook; References; 6 Ninesilica: A Homogeneous MPSoC Approach for SDR Platforms; 6.1 Introduction; 6.2 Ninesilica Architecture; 6.2.1 Network-on-Chip; 6.2.2 Power Management; 6.2.3 I/O Management; 6.2.4 Hardware Implementation; 6.3 Cases Studies; 6.3.1 WCDMA; 6.3.2 OFDM; 6.4 Analysis of Results.

This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. Coverage includes architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability. Describes a computer engineering approach to SDR baseband processing hardware; Discusses implementation of numerous compute-intensive signal processing algorithms on single and multicore platforms; Enables deep understanding of optimization techniques related to power and energy consumption of multicore platforms using several basic and high-level performance indicators; Includes prototyping details of single and multicore platforms on ASICs and FPGAs.