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Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications / Taimur Rabuske, Jorge Fernandes.

By: Rabuske, Taimur.
Contributor(s): Fernandes, Jorge.
Material type: materialTypeLabelE-bookSeries: (Analog Circuits and Signal Processing).Publisher: Cham : SpringerDescription: 1 recurso en línea (173 páginas).ISBN: 3319396242; 9783319396248.Subject: Convertidores analógicos-digitalesOnline resources: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Contents:
Preface; Contents; 1 Introduction ; Contents; 1.1 Background; 1.2 Research Goals; 1.3 Book Outline; 1.4 Original Contributions; 1.5 Final Remarks; References; 2 ADCs for Low-Voltage Low-Power Applications ; Contents; 2.1 Introduction; 2.2 Sampling and Quantization; 2.3 Search Methods for Nyquist ADCs; 2.3.1 Direct Search (Flash ADCs); 2.3.2 Binary Search (SAR ADCs); 2.3.3 Pipelined Binary Search (Pipeline ADCs); 2.3.4 Summary; 2.4 The SAR ADC; References; 3 Review of SAR ADC Switching Schemes ; Contents; 3.1 Introduction; 3.2 Operation Modes of Charge-Based SAR ADCs.
3.2.1 The Charge Redistribution Principle3.2.2 The Charge Sharing Principle; 3.3 Charge Redistribution Switching Schemes; 3.3.1 Conventional Switching; 3.3.2 Monotonic or "Set-and-Down'' Switching; 3.3.3 vcm-Based Capacitor Switching; 3.3.4 Tri-Level Capacitor Switching; 3.4 Charge Sharing Switching Scheme; 3.5 Comparison of Reviewed Switching Schemes; 3.6 State of the Art in CS-ADCs; 3.6.1 Craninckx and van der Plas ch3:Craninckx2007; 3.6.2 Giannini et al. ch3:Giannini2008; 3.6.3 Tsai et al. ch3:Tsai2011; 3.6.4 Malki et al. ch3:Malki2012,ch3:Malki2014; 3.6.5 Summary.
4.6.1 Differential Nonlinearity4.6.2 Integral Nonlinearity; 4.6.3 ENOB; 4.6.4 Model Verification; 4.6.5 Discussion; 4.7 Errors Caused by Noise; References; 5 Noise-Aware Synthesis and Optimization of Voltage Comparators ; Contents; 5.1 Introduction; 5.2 Review on Comparator Noise Calculation; 5.3 Comparator Noise Measurement; 5.4 Multi-Objective Optimization Framework; 5.5 Design Example; 5.6 Results; 5.7 Discussion; References; 6 An 8-Bit 0.35-V CS-ADC with Comparator Offset Auto-Zero and Voltage Boosting; Contents; 6.1 Introduction; 6.2 CS-ADC with Background Comparator Offset Auto-Zeroing.
6.2.1 Operation Principle of the Proposed CS-ADC6.2.2 Background Comparator Offset Self-Zeroing; 6.3 SAR ADC Implementation; 6.3.1 Self-Calibrated Comparator; 6.3.2 Local Voltage Boosting; 6.3.3 Full-Custom Self-Timed SAR Controller; 6.3.4 TH and DAC; 6.4 Experimental Results; 6.5 Discussion; References; 7 A 9-Bit 0.6-V CS-ADC with a MOSCAP-DAC; Contents; 7.1 Introduction; 7.2 CS-ADC with a MOSCAP-Based DAC; 7.3 SAR ADC Implementation; 7.3.1 Comparator; 7.3.2 Configurable TH with Boost-and-Bootstrap Switches; 7.3.3 Voltage Boosters; 7.3.4 DAC Cells; 7.4 Experimental Results; 7.5 Discussion.
Appendix: Voltage and Energy in CR ADCsModels for Voltage and Energy in CR ADCs; Simplified Voltage Model for CR DACs; General Voltage Model for CR DACs; Codes; References; 4 Effects of Nonidealities on the Performance of CS-ADCs ; Contents; 4.1 Introduction; 4.2 Trajectory of the DAC Voltage in a CS-ADC; 4.3 Analog-to-Digital Conversion Gain; 4.4 Errors Caused by Mismatch; 4.4.1 Mismatch Between TH Capacitors; 4.4.2 Mismatch Between TH and Total DAC Capacitance; 4.4.3 Mismatch Between DAC Capacitors; 4.5 Errors Caused by Parasitics; 4.6 Errors Caused by Comparator Offset.
Abstract: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
LIBRO-E NO PRÉSTAMO LIBRO-E NO PRÉSTAMO Madrid Digital Acceso Electrónico (UEM) Ciencias e Ingeniería TK7887.6 R338 2016 EB (Browse shelf(Opens below)) Acceso electrónico eBook.20022077
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Appendix: Frequency-Dependency of C(V) in MOSCAPs.

SpringerLink Springer Engineering eBooks 2017 English+International

Preface; Contents; 1 Introduction ; Contents; 1.1 Background; 1.2 Research Goals; 1.3 Book Outline; 1.4 Original Contributions; 1.5 Final Remarks; References; 2 ADCs for Low-Voltage Low-Power Applications ; Contents; 2.1 Introduction; 2.2 Sampling and Quantization; 2.3 Search Methods for Nyquist ADCs; 2.3.1 Direct Search (Flash ADCs); 2.3.2 Binary Search (SAR ADCs); 2.3.3 Pipelined Binary Search (Pipeline ADCs); 2.3.4 Summary; 2.4 The SAR ADC; References; 3 Review of SAR ADC Switching Schemes ; Contents; 3.1 Introduction; 3.2 Operation Modes of Charge-Based SAR ADCs.

3.2.1 The Charge Redistribution Principle3.2.2 The Charge Sharing Principle; 3.3 Charge Redistribution Switching Schemes; 3.3.1 Conventional Switching; 3.3.2 Monotonic or "Set-and-Down'' Switching; 3.3.3 vcm-Based Capacitor Switching; 3.3.4 Tri-Level Capacitor Switching; 3.4 Charge Sharing Switching Scheme; 3.5 Comparison of Reviewed Switching Schemes; 3.6 State of the Art in CS-ADCs; 3.6.1 Craninckx and van der Plas ch3:Craninckx2007; 3.6.2 Giannini et al. ch3:Giannini2008; 3.6.3 Tsai et al. ch3:Tsai2011; 3.6.4 Malki et al. ch3:Malki2012,ch3:Malki2014; 3.6.5 Summary.

4.6.1 Differential Nonlinearity4.6.2 Integral Nonlinearity; 4.6.3 ENOB; 4.6.4 Model Verification; 4.6.5 Discussion; 4.7 Errors Caused by Noise; References; 5 Noise-Aware Synthesis and Optimization of Voltage Comparators ; Contents; 5.1 Introduction; 5.2 Review on Comparator Noise Calculation; 5.3 Comparator Noise Measurement; 5.4 Multi-Objective Optimization Framework; 5.5 Design Example; 5.6 Results; 5.7 Discussion; References; 6 An 8-Bit 0.35-V CS-ADC with Comparator Offset Auto-Zero and Voltage Boosting; Contents; 6.1 Introduction; 6.2 CS-ADC with Background Comparator Offset Auto-Zeroing.

6.2.1 Operation Principle of the Proposed CS-ADC6.2.2 Background Comparator Offset Self-Zeroing; 6.3 SAR ADC Implementation; 6.3.1 Self-Calibrated Comparator; 6.3.2 Local Voltage Boosting; 6.3.3 Full-Custom Self-Timed SAR Controller; 6.3.4 TH and DAC; 6.4 Experimental Results; 6.5 Discussion; References; 7 A 9-Bit 0.6-V CS-ADC with a MOSCAP-DAC; Contents; 7.1 Introduction; 7.2 CS-ADC with a MOSCAP-Based DAC; 7.3 SAR ADC Implementation; 7.3.1 Comparator; 7.3.2 Configurable TH with Boost-and-Bootstrap Switches; 7.3.3 Voltage Boosters; 7.3.4 DAC Cells; 7.4 Experimental Results; 7.5 Discussion.

Appendix: Voltage and Energy in CR ADCsModels for Voltage and Energy in CR ADCs; Simplified Voltage Model for CR DACs; General Voltage Model for CR DACs; Codes; References; 4 Effects of Nonidealities on the Performance of CS-ADCs ; Contents; 4.1 Introduction; 4.2 Trajectory of the DAC Voltage in a CS-ADC; 4.3 Analog-to-Digital Conversion Gain; 4.4 Errors Caused by Mismatch; 4.4.1 Mismatch Between TH Capacitors; 4.4.2 Mismatch Between TH and Total DAC Capacitance; 4.4.3 Mismatch Between DAC Capacitors; 4.5 Errors Caused by Parasitics; 4.6 Errors Caused by Comparator Offset.

This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.

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