Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.