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Introduction to Noise-Resilient Computing / by Svetlana N. Yanushkevich, Seiya Kasai, Golam Tangim, A.H. Tran

By: Yanushkevich, Svetlana N., autor
Contributor(s): Kasai, Seiya, autor | Tangim, Golam, autor | Tran, A. H., autor
Material type: materialTypeLabelE-bookSeries: (Synthesis Lectures on Digital Circuits & Systems, 1932-3174).Publisher: Cham : Springer International Publishing, 2013Edition: 1st edition 2013.Description: 1 recurso en línea (XIX, 132 páginas).ISBN: 9783031798559.Subject: Tolerancia a los fallos (Informática)Online resources: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Contents:
Introduction to probabilistic computation models -- Nanoscale circuits and fluctuation problems -- Estimators and Metrics -- MRF Models of Logic Gates -- Neuromorphic models -- Noise-tolerance via error correcting -- Conclusion and future work.
Summary: Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work.
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
LIBRO-E NO PRÉSTAMO LIBRO-E NO PRÉSTAMO Madrid Digital Acceso Electrónico (UEM) Ciencias e Ingeniería QC176.8.N35 2013 EB (Browse shelf(Opens below)) Acceso electrónico eBook.01112101
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Introduction to probabilistic computation models -- Nanoscale circuits and fluctuation problems -- Estimators and Metrics -- MRF Models of Logic Gates -- Neuromorphic models -- Noise-tolerance via error correcting -- Conclusion and future work.

Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work.

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