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Logic Synthesis and SOC Prototyping : RTL Design using VHDL / by Vaibbhav Taraate.

By: Taraate, Vaibbhav, autor
Contributor(s): SpringerLink (Online service)
Material type: materialTypeLabelE-bookPublisher: Singapore : Springer Singapore : Imprint Springer, 2020Edition: First edition.Description: 1 recurso en línea (XIX, 251 páginas).ISBN: 9789811513145.Subject: Sistemas embebidosOnline resources: Acceso a este recurso digital (usuarios Universidad Europea de Madrid)Digital Resources
Contents:
Introduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA. .
In: Springer eBooksAbstract: This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
LIBRO-E NO PRÉSTAMO LIBRO-E NO PRÉSTAMO Madrid Digital Acceso Electrónico (UEM) Ciencias e Ingeniería TK7895.E42 2020 EB (Browse shelf(Opens below)) Acceso electrónico eBook28022119
Total holds: 0

Introduction -- ASIC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASIC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA. .

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

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