Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors / by Hans Reyserhove, Wim Dehaene.
By: Reyserhove, Hans, autor
Contributor(s): SpringerLink (Online service)
| Dehaene, Wim, autor
Material type:
E-bookSeries: (Engineering (Springer-11647)).Publisher: Cham : Springer International Publishing : Imprint: Springer, 2019Description: 1 recurso en línea (XXIV, 209 páginas) : 141 ilustraciones, 80 ilustraciones a color.ISBN: 9783030124854.Subject: Circuitos integrados -- Diseño y construcción
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | |
|---|---|---|---|---|---|---|---|---|
LIBRO-E NO PRÉSTAMO
|
Madrid Digital Acceso Electrónico (UEM) | Ciencias e Ingeniería | TK7874 2019 EB (Browse shelf(Opens below)) | Acceso electrónico | eBooks24062771 |
Chapter 1. Energy-Efficient Processors: Challenges and Solutions -- Chapter 2. Near-Threshold Operation: Technology, Building Blocks and Architecture -- Chapter 3. Efficient VLSI Design Flow -- Chapter 4. Ultra-Low Voltage Microcontrollers -- Chapter 5. Error Detection and Correction -- Chapter 6. Timing Error-Aware Microcontroller -- Chapter 7. Conclusion.
This book enables readers to achieve ultra-low energy digital system performance. The author's main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy. Presents a full bottom-up micro-electronics approach: circuit-level, design strategy and CAD automation, architecture optimization Motivates discussion with simulation results and/or measurements in an advanced nanometer CMOS process Compares traditional circuit/design/architecture techniques and state-of-the-art, setting the landscape of current best performance and how it can be improved.
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