Functional Verification of Dynamically Reconfigurable FPGA-based Systems / by Lingkan Gong, Oliver Diessel.
By: Gong, Lingkan, autor
Contributor(s): Diessel, Oliver, autor
Material type:
E-bookSeries: (Engineering (Springer-11647)).Publisher: Cham : Springer International Publishing, 2015Description: 1 recurso en línea (XXI, 216 páginas 72 ilustraciones, 48 ilustraciones a color.).ISBN: 9783319068381.Subject: Dispositivos FPGAs
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | |
|---|---|---|---|---|---|---|---|---|
LIBRO-E NO PRÉSTAMO
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Madrid Digital Acceso Electrónico (UEM) | Ciencias e Ingeniería | TK7895.G36 2015 EB (Browse shelf(Opens below)) | Acceso electrónico | eBook.12112836 |
Introduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References.
This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc. ...).
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