Introduction -- Recent Trends in Bias Temperature Instability -- Charge trapping phenomena in MOSFETS: From Noise to Bias Temperature Instability -- Atomistic Simulations on Reliability -- On-chip characterization of statistical device degradation -- Circuit Resilience Roadmap -- Layout Aware Electromigration Analysis of Power/Ground Networks -- Power-Gating for Leakage Control and Beyond -- Soft Error Rate and Fault Tolerance Techniques for FPGAs.

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.